1. Field of the Invention
The present invention relates to a nonvolatile memory, and more particularly, to system and method for programming a nonvolatile memory.
2. Discussion of the Related Art
Generally, in using nonvolatile semiconductor memory devices, such as EEPROM and flash EEPROM, for mass storage media, the most difficult-to-overcome drawback is that cost-per-bit of the memories is too expensive. In order to solve such a problem, studies on multibit-per-cell have been recently proposed. The packing density of a background art nonvolatile memory corresponds to the number of memory cells in one to one fashion. Meanwhile, the multibit-per-cell stores data of over two bits in one memory cell, enhancing the density of data on the same chip area, without reducing the size of the memory cell. For the multibit-per-cell, more than three threshold voltage levels should be programmed on the respective memory cells. For instance, in order to store data of over two bits for every cell, the respective cells must be programmed in 2.sup.2, that is, four, threshold levels. Here, the four threshold levels correspond to logic states 00, 01, 10, and 11, respectively.
In the multi-level program, the most critical problem is that the respective threshold voltage levels have a statistic distribution. The distribution value is about 0.5V. As the distribution is reduced more by precisely adjusting the respective threshold levels, more levels can be programmed, which in turn increases the number of bits for every cell. To reduce the voltage distribution, there is a method of performing programming by repeating programming and verification. According to this method, a series of program voltage pulses are applied to the cells in order to program the nonvolatile memory cell in intended threshold levels. To verify whether the cell reaches an intended threshold level, reading is performed between the respective voltage pulses. During verification, when the verified threshold level reaches the intended threshold level, programming stops. In the method of repeating programming and verification, it is hard to reduce the error distribution of the threshold level due to the limited pulse width of a program voltage. In addition, the algorithm of repeating programming and verification is implemented with a circuit, increasing the area of peripheral circuits of the chip. Furthermore, the repetitive method elongates the time to program. In order to solve such a drawback, R. Cernea of SunDisk Co., Ltd. suggested a method of performing programming and verifying simultaneously in U.S. Pat. No. 5,442,842 registered on Jun. 6, 1995.
FIG. 1a illustrates the symbol and circuit diagram of the nonvolatile memory (EEPROM) disclosed by Cernea, and FIG. 1b is a graph showing a programming principle of the nonvolatile memory of FIG. 1a.
Referring to FIG. 1a, the nonvolatile memory cell is composed of a control gate, floating gate, source, channel region, and drain. When a voltage sufficient to cause programming is applied to control gate and drain, currents flow between drain and source. When the thus flowing currents are compared with a reference current and reach a value equal to or smaller than the reference current, a programming completion signal is produced. According to this background art, verification is automatically performed at the same time of programming, compensating for the drawbacks of the repetitive method in which programming and verification are repeated. However, in the Cernea's method, the threshold voltage levels are not controlled by the voltages applied to respective electrodes on field effect transistors in the memory cell. And, in U.S. Pat. No. 5,043,940 registered on Aug. 27, 1991, multi-level programming has been performed in such a manner that the voltage applied to the respective ports of a memory cell is fixed, and reference currents corresponding to the respective levels are varied. In this method, as shown in FIG. 1b, reference currents for detection have no explicit relation with the cell threshold voltages, and are not linear therewith.
And, as shown in FIG. 2a, when the programming and erasing of the memory cell is repeated numerous times in the background art second method, a tunnel oxide film between the floating gate and the channel of the cell is physically degraded, with an increased charges trapped therein, that gradually reduces a program level. And, as shown in FIG. 2b, a probability density distribution of each threshold voltage corresponding to each multi-level also is not even, and becomes the more wider as the program times are increased, leading to a reduction of a reading allowance.
The aforementioned background art method for programming a nonvolatile memory has the following problems.
First, in the method of programming by repeating programming and verification, the degradation of the tunnel oxide film as a number of program/erasure is increased, with a gradual decrease of program level and a wider distribution of each threshold voltage corresponding to each multi-level which reduces a reading allowance, drops a program reliability.
Second, in the method of programing by varying a reference current corresponding to each level, since a direct and effective multi-level control is difficult, an effective programing is not possible.